Release Notes for MPLAB® SIM Simulator
MPLAB® IDE v8.56
DLL and Firmware versions:
| Sim12.dll | v2.10.00.00 | |
| Sim16.dll | v2.10.01.01 | |
| MPSim.dll | v8.62.01.0 | (SIM17) |
| Sim18.dll | v3.20.00.00 | |
| dsPicSim30.dll | v4.30.00.00 | (SIM30) |
| Sim32.dll | v0.00.10.06 |
August 13, 2010
Table of Contents
5 Repairs and Enhancements Made in v8.56
Click the link below to see device support for the simulator (SIM).
This tool has been tested using the following operating systems:
32-Bit: Windows® 2000 SP4, Windows XP SP2, Windows Vista™ and Windows 7 OSs
64-Bit: Windows XP 64, Windows Vista 64 and Windows 7 64 OSs
NOTE: Windows NT® and Windows 98/ME OSs are NOT supported.
The following documents may be found on our website or MPLAB IDE CD-ROM:
· MPLAB IDE User's Guide (DS51519)
· MPLAB IDE Quick Start Guide (DS51281)
· MPLAB IDE Quick Chart (DS51410)
On-line help (Help>Topics) is also available for this tool:
· Debuggers>MPLAB SIM - hlpMPLABSIM.chm
None.
|
Summary |
Device Affected |
|
|
SIM-727 |
Selecting any i/o pin as an asynchronous stimulus causes Simulator errors for PIC16F1946/47 |
PIC16F1946, PIC16F1947, PIC16LF1946, PIC16LF1947 |
|
SIM-695 |
When INTCON1 <NSTDIS> is set (Nested Interrupt Disabled), any write to SR will cause SR's DC bit to clear automatically |
dsPIC30F3013, dsPIC30F6013A, dsPIC30F6014A |
|
SIM-692 |
Unable to trigger ICx Interrupt for PIC24F04KA200 and PIC24F16KA102 family |
PIC24F04KA200 and PIC24F16KA102 family |
|
SIM-680 |
Unexpected behavior when pre/post-decrement or pre/post-increment a destination register that is part of the SUBR equation (example: subr.w w6, w8, [w6--]) |
PIC24FJ256GB110 |
|
SIM-670 |
ADC of dsPIC33FJXXGSXXX devices is not triggered when trigger source is selected as Timer2 |
dsPIC33F GS family devices |
|
SIM-627 |
CN8, CN9, and CN10 Pins Do Not Generate Interrupts in Response to a Change of State on the Corresponding Pin for PIC24HJXXXGPX04 |
PIC24HJ32GP304, PIC24HJ64GP204, PIC24HJ64GP504, PIC24HJ128GP204, PIC24HJ128GP504, PIC24HJ16GP304 |
|
SIM-591 |
None of the CNx pins generate an interrupt in response to a change of state on the corresponding pin |
dsPIC33FJ32GS406, dsPIC33FJ32GS606, dsPIC33FJ32GS608, dsPIC33FJ32GS610, dsPIC33FJ64GS406, dsPIC33FJ64GS606, dsPIC33FJ64GS608, dsPIC33FJ64GS610 |
|
SIM-589 |
Unable to use CN0, CN2, CN3, CN29 and CN30 signals in the Stimulus file for PIC24HJXXXGPX02 and PIC24HJXXXGPX04 devices |
PIC24HJ32GP302, PIC24HJ32GP304, PIC24HJ64GP202, PIC24HJ64GP204, PIC24HJ64GP502, PIC24HJ64GP504, PIC24HJ128GP202, PIC24HJ128GP204, PIC24HJ128GP502, PIC24HJ128GP504 |
|
SIM-572 |
Getting "Pin(s) (0x4000) on PORTB can not be stimulated due to being controlled by the A/D converter" message when INT1 is mapped to certain RP (RB) pins on some dsPIC33FJXXMC devices. |
dsPIC33FJ32MC302, dsPIC33FJ32MC304, dsPIC33FJ64MC202, dsPIC33FJ64MC204, dsPIC33FJ128MC202, dsPIC33FJ128MC204, dsPIC33FJ64MC802, dsPIC33FJ64MC804, dsPIC33FJ128MC802, dsPIC33FJ128MC804 |
|
SIM-549 |
Change notification interrupts such as CN69, CN56 not generated for PIC24FJ64GB1XX devices |
PIC24FJ64GB106- Possibly other devices in the same family |
|
SIM-731 |
APFCON0.CCP1SEL has no affect on the output pin of CCP1 module. |
PIC16F1826 |
|
SIM32-179 |
Second instruction after a Return is skipped |
PIC32 |
The following is a list of known problems. For information on common problems, error messages and limitations, please see Troubleshooting in the online help file for MPLAB SIM (hlpMPLABSIM.chm).
Building a project for the simulator under Debug mode will cause non-required resources to be used. This may cause code without proper paging or banking operations not to function in this mode for 8 bit devices.
At this time the PIC32 simulator has some variations in cycle accuracy when compared to the real silicon. The PIC32 simulator does not simulate things like the cache, pre-fetch buffer, wait states and Bus matrix divisions. The Bus matrix is fixed at 1:1 with the processor clock. This can have an effect of making algorithm timing loops appear to be slower than they are in real silicon. Each instruction is accurate in execution and timing in itself.
|
Key |
Summary |
Device Affected |
|
SIM-98 |
[PIC24FJ]:Selection of XT/HS/EC as clock source do not prevent using RC15 and RC12 as GPIO's |
PIC24FJXXX devices: Applicable to other 16 bit devices (dsPIC33F/24H) as well |
|
SIM-188 |
PORTD inputs works as digital when they are turned analog |
PIC18F4480, PIC18F458, PIC18F4580, PIC18F4585, PIC18F4680, PIC18F4682 and PIC18F4685 |
|
SIM-191 |
Interrupt on change works when the pins are analog. |
PIC12F683 |
|
SIM-211 |
Write 0XFF to LATG will write PORTG<5:7> bits, which are not expected to be controlled by LATG. |
|
|
SIM-372 |
Flash data row erase happens even if the specified row erase sequence IS not followed IN SIMULATOR for 12F519 device |
PIC12F519 |
|
SIM-388 |
Request to implement IOFS bit of OSCCON register similar to PLL-Lock bit of SIM30 for Midrange and PIC18 devices |
Midrange and Enhanced Device Family |
|
SIM-404 |
Value of the STKPTR wraps around after the Stack Overflow, even when the configuration bit "Stack Overflow Reset" (STVR=OFF) is disabled. |
PIC18F1220 |
|
SIM-413 |
TMR3H register doesn't get updated in the watch window even after doing a read on the timer TMR3L register in the code when cofigured for 8-bit read/write mode. |
PIC18F family |
|
SIM-414 |
Total ADC conversion priod in simulator is 9.5Tad instead of 10Tad for PIC16LF72X devices |
PIC16LF/F72X Family |
|
SIM-420 |
When using the simulator with PIC16F886, PCLATH does not update correctly |
|
|
SIM-423 |
Flash and EEPROM write/Erase operation does not work for many options for PIC24FKA devices |
PIC24FXXKA |
|
SIM-443 |
Flash memory write routines don't actually erase block before writing data in the simulator for devices such as PIC16F883, PIC16F884, 886 etc |
PIC16F88X Family devices, PIC16F874A, PIC16F877A |
|
SIM-446 |
Simulator causes reset or behaves incorrectly if instruction at 4th cycle lag of stack error trap happens to be stack related instruction for 16 bit devices |
PIC16-Bit Family |
|
SIM-447 |
Unable to Map Crossbar I/O T3CK to RPx pin for dsPIC33FJ32GP204, dsPIC33FJ32MC204, dsPIC33FJ16GP304, dsPIC33FJ16MC304 devices |
dsPIC33FJ32GP204, dsPIC33FJ32MC204, dsPIC33FJ16GP304, dsPIC33FJ16MC304 |
|
SIM-448 |
Inconsistent T3CK Mapping Behavior for dsPIC33FJ12GP201 and dsPIC33FJ12MC201 devices |
dsPIC33FJ12GP201, dsPIC33FJ12MC201 |
|
SIM-449 |
Signals from Logic Analyzer Window disappeared after switching from device to device |
All |
|
SIM-450 |
Unable to trigger interrupt from Sleep after reset for dsPIC33FJ32GP204, dsPIC33FJ12GP201, dsPIC33FJ16GP304 |
dsPIC33FJ32GP204, dsPIC33FJ12GP201, dsPIC33FJ16GP304 |
|
SIM-457 |
Unexpected behavior when setting/clearing an unmapped peripheral pin from the stimulus (INT1, INT2, TxCK) for dsPIC33FJ PPS Devices |
dsPIC33FJ Peripheral Devices |
|
SIM-465 |
Animate crashes MPLAB IDE when logic analyzer window is open |
All |
|
SIM-466 |
Reset value of STKPTR does
not match |
PIC16F19XX |
|
SIM-469 |
In Simulator, STKPTR wraps upon overflow and underflow for PIC16F19XX device which is not expected as per DOS |
PIC16F19XX |
|
SIM-473 |
[PIC16F72X ] Timer gated mode operations such as single pulse, togle mode are not implemented in simulator for PIC16F72X devices |
PIC16F72X devices |
|
SIM-474 |
[PIC16F72X} Timer1 gated mode operation does not work when gate source is other than T1G input for PIC16F72X family devices |
PIC16F72X |
|
SIM-476 |
|
16 bit devices |
|
SIM-477 |
SIM18 does not behave properly when using RD16 bit in T1CON/T3CON registers in Timers 1 and 3 |
PIC18F4450, PIC18F2450, PIC18F family |
|
SIM-479 |
Bits IDLEN, OSTS, SCS1 & SCS0 are not implemented in .dev file. |
PIC18F85J90 Family |
|
SIM-480 |
Input Capture2 to 5 does not respond to input and capture never happens for PIC24F PPS devices with Ehanced capture module |
PIC24FJ128GA106-Possibly other PIC24F PPS devices with Enhanced capture |
|
SIM-484 |
Interrupt occurs due to to Interrupt on Change pin even when the port pins are made Analog for PIC16F677 |
PIC16F677 |
|
SIM-486 |
Stepping over a MACRO causes MPSIM to hang |
PIC12F683 |
|
SIM-489 |
[PIC16-E] MPLAB Sim reports it as invalid ADC channel when CVref/FVR or Temp band gap is selected as analog input channel for PIC16F193X devices |
PIC16F19XX Family |
|
SIM-490 |
Timer 0 does not increment when the clock source is T0CKI in PPS devices |
PIC18F46J11, PIC18F46J50 |
|
SIM-492 |
Improper functioning of Timer3 on PIC18F46J11 and PIC18F46J50 PPS devices. |
PIC18F46J11, PIC18F46J50 |
|
SIM-495 |
Unable to simulate PWM module on PIC18F46J11 and PIC18F46J50 PPS devices |
PIC18F46J11, PIC18F46J50 |
|
SIM-496 |
Unable to simulate Comparator module on PIC18F46J11 and PIC18F46J50 PPS devices. |
PIC18F46J11, PIC18F46J50 |
|
SIM-497 |
[19XX] WDT postscaler above 1:65536 always provide ~2 sec time out period irrespective of postscaler bit settings for PIC16F19XX devices |
PIC16F19XX Family |
|
SIM-499 |
[19XX] WDT can be enabled by software even though it is disabled in configuration register for PIC16F19XX devices |
PIC16F19CX family devices |
|
SIM-500 |
Various options of WDT enable/disable through configuration fuse settings are not implemented in simulator for PIC16F193X devices |
PIC16F193X |
|
SIM-506 |
WDT prescaler works on OPTION_REG for 19XX devices even though prescaler setting in the OPTION REG is only applicable to Timer0 |
PIC16F19XX |
|
SIM-509 |
Oscillator control I/O operation on PORTA is incorrect for PIC16F19XX devices |
PIC16F193X |
|
SIM-510 |
Interrupt On Change do not occur on RB0 to RB3 for PIC16F19XX devices |
PIC16F19XX |
|
SIM-511 |
IOCBFx bits of IOCBF register does not set when interrupt on change occurs for PIC16F19XX devices |
PIC16F19XX |
|
SIM-512 |
Edge selection for Interrupt On Change is ignored in simulator for PIC16F19XX devices. |
PIC16F19XX |
|
SIM-518 |
Load program flash "write latches" operation will also write program flash for PIC16F19XX |
PIC16F19XX |
|
SIM-519 |
Attempt to read from configuration memory will read from program flash in simulator for PIC16F19XX devices |
PIC16F19XX |
|
SIM-520 |
First instruction after BSF EECON1,RD is ignored in simulator for PIC16F19XX |
PIC16F19XX |
|
SIM-533 |
CLONE -[PIC16F19XX} Timer1 gated mode operation does not work when gate source is other than T1G input for PIC16F19XX family devices |
PIC16F19XX |
|
SIM-534 |
CLONE -[PIC16F19XX ] Timer gated mode operations such as single pulse, toggle mode are not implemented in simulator for PIC16F19XX devices |
PIC16F19XX devices |
|
SIM-535 |
Clearing TXIF flag at the second cycle of RETFIE instruction will still trigger interrupt again for PIC16F19XX in simulator |
PIC16F19XX-may be other devices too |
|
SIM-536 |
CCPx module does not work on TMR4 or TMR6 in PWM mode for PIC16F19XX devices |
PIC16F19XX |
|
SIM-537 |
like PIC18F devices, request to implement dead time for PWM for PIC16F19XX devices |
PIC16F19XX |
|
SIM-539 |
PWM auto shut down feature is not implemented for PIC16F19XX devices |
PIC16F19XX |
|
SIM-543 |
ECCP1 pin assignment is incorrect for PIC16F1936 and 1933 devices. As a result, PWM output is not reflected in the PORTB pins |
PIC16F1936 and 1933 |
|
SIM-545 |
In MPLAB IDE version 8.20 option for sync 4 is missing from asynchronous stimulus page for the PIC24FJ128GB106 device |
PIC24FJ128GB106 |
|
SIM-546 |
EUSART shows incorrect timing for 16-bit asynchronous transmit of 1-byte. |
PIC16F688 |
|
SIM-548 |
[SCL file] - With Timer 2 Clock (T2CK) pin remapped to RP8 (i.e. RB8) pin, clock signal is not generated properly when 'T2CK' signal name is used in the SCL file instead of 'RB8' signal name; same issue with T3CK, T4CK & T5CK |
PIC24HJ128GP202; dsPIC33FJ16GS402, PIC24FJ256GA110, PIC24FJ192GA110, PIC24FJ128GA110 |
|
SIM-554 |
Timer operating in external clock mode misses edge on certain conditions for 16 bit devices |
16 bit device Family |
|
SIM-556 |
USB TRISF bits on the PIC18F87J50 family should be unimplemented, but can write a '1' to them |
PIC18F87J50 family |
|
SIM-566 |
Stimulus incorrectly providing trigger to INT0 pin for PIC24F_PPS devices.This is after code is executed once and reset is performed |
PIC24FJXXGA004/002. |
|
SIM-571 |
[OC w/ Dedicated Timer] Simulation of PWM mode of the Output Compare module doesn't work for PIC24FJ256GB110 family & PIC24FJ256GA110 family |
PIC24FJ256GB110 family (PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106), and PIC24FJ256GA110 family (PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106) |
|
SIM-586 |
PORTB-RB0 can be used as digital I/O without setting port as Digital in simulator for PIC24FJXXGA002 , XXGA004 |
PIC24FJXXGA002 , PIC24FXXGA004 |
|
SIM-587 |
ADC simulation for band gap ref- AN15/VBG is not simulated for PIC24FJXXGA002/004 devices |
PIC24FJXXGA002/004 Possibly other PIC24F devices |
|
SIM-590 |
OCFLT bit in OCxCON register is read-only, but still can be set to 1 in software |
dsPIC33FJ32GS406, dsPIC33FJ32GS606, dsPIC33FJ32GS608, dsPIC33FJ32GS610, dsPIC33FJ64GS406, dsPIC33FJ64GS606, dsPIC33FJ64GS608, dsPIC33FJ64GS610 |
|
SIM-594 |
Missing File Register Window for Dual Port RAM for Devices dsPIC33FJ64GS606, dsPIC33FJ64GS608, dsPIC33FJ64GS610 |
dsPIC33FJ64GS606, dsPIC33FJ64GS608, dsPIC33FJ64GS610 |
|
SIM-596 |
Stimulus Register Trace does not function on Midrange/Baseline devices using HI-TECH compiler. |
10F222... midrange/baseline |
|
SIM-601 |
Flash Erase/Read/Write is not implemented for PIC18F87K90 device. |
PIC18F87K90 |
|
SIM-602 |
[High-Speed Analog Comparator] CMPSTAT bit of CMPCONx register not set & CMPx Interrupt not generated when CMPx output is high, though the interrupts are enabled |
dsPIC33FJ32GS606, dsPIC33FJ32GS608, dsPIC33FJ32GS610, dsPIC33FJ64GS606, dsPIC33FJ64GS608, dsPIC33FJ64GS610 |
|
SIM-607 |
Stimulus Incorrectly set IFS1 (#INT1IF) bit for dsPIC33FJ32GSXXX and dsPIC33FJ64GSXXX Devices |
dsPIC33FJ32GS406/606/608/610, dsPIC33FJ64GS406/606/608/610 |
|
SIM-611 |
[PIC16F182X] Flash read of configuration space does not return configuration data, instead returns program memory data. |
[PIC16F182X] |
|
SIM-612 |
[Stimulus-sim database] Unsupported analog channels are added to stimulus files for several dsPIC33FXXXMCXX2 and MCXX4 devices |
dsPIC33FJ128MC202, dsPIC33FJ32MC302, dsPIC33FJ64MC202, dsPIC33FJ64MC204, dsPIC33FJ128MC204, dsPIC33FJ32MC304, dsPIC33FJ64MC802, dsPIC33FJ64MC804, dsPIC33FJ128MC804 |
|
SIM-613 |
[High Speed Analog Comparator] C1OUT and C2OUT signals/channels must be removed from the Logic Analyzer since they are not physical pins on the 32GSXXX and 64GSXXX devices |
dsPIC33FJ32GS606, dsPIC33FJ32GS608, dsPIC33FJ32GS610, dsPIC33FJ64GS606, dsPIC33FJ64GS608, dsPIC33FJ64GS610 |
|
SIM-614 |
[High Speed Analog Comparator] Comparator output signals as well as the port pins to which they are remapped are always low in the logic analyzer for 06GS202 and PIC16GS50X |
dsPIC33FJ06GS202, dsPIC33FJ16GS502, dsPIC33FJ16GS504 |
|
SIM-616 |
[Stimulus] DMA registers injection on "demand" need to be removed for 16 bit devices |
16 bit devices |
|
SIM-617 |
[stimulus] ADC1BUF1 to ADC1BUFF to be removed from register injection for devices such as dsPIC33FJ16MC304, 32MC204 etc |
dsPIC33FJ16MC304, 32MC204 |
|
SIM-618 |
[High-Speed Analog Comparator] CMPSTAT bit of CMPCON3 and CMPCON4 registers not set/cleared correctly in accordance with the polarity of the comparator output in dsPIC33FJ16GS502/4 |
dsPIC33FJ16GS502, dsPIC33FJ16GS504 |
|
SIM-622 |
Toggle on compare match of CCP functions incorrectly when the prescaler of the Timer used is greater than 1:1. |
PIC18F452 |
|
SIM-623 |
CMP4C and CMP4D signals are absent in the Stimulus Controller for dsPIC33FJ16GS504 |
dsPIC33FJ16GS504 |
|
SIM-628 |
TMR2 does not increment on Fosc/4 when Prescalar of 1:16 is used on PIC16F690 |
PIC16F690 |
|
SIM-632 |
Cannot set RB15-RB12 for dsPIC33F32MC302/304, dsPIC33F64MCX02/X04, and dsPIC33F128MCX02/X04 |
dsPIC33F32MC302/304, dsPIC33F64MCX02/X04, and dsPIC33F128MCX02/X04 |
|
SIM-633 |
DMA transfer from ICxBUF to DMA RAM does not occur when DMA request is ICx itself. If DMA req source is other than ICx, it works |
16 bit devices |
|
SIM-635 |
Missing CCP1 pin in Logic Analyzer and Stimulus Pin selection. |
PIC16F818, PIC16F87, PIC16F88, PIC16F819, PIC16F887 |
|
SIM-636 |
PIC16F946 RCREG only has the option of "Demand", it should be a "message" based stimulus instead. |
PIC16F946 |
|
SIM-638 |
When changing devices, need to refresh the stimulus window. If you change to a new device it will still show the pins from the old device. |
All |
|
SIM-639 |
[12F615] CCP1 pin is missing from Stimulus controller |
12F615, 12HV615 |
|
SIM-643 |
UART3 and UART4 modules don't function in PIC24FJ256GB110 family and PIC24FJ256GA110 family of devices |
PIC24FJ256GB110 family (PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106), and PIC24FJ256GA110 family (PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106) |
|
SIM-644 |
ECCP2 is missing from stimulus window Clock Stimulus Pin drop down. |
PIC18F8722 |
|
SIM-645 |
Cannot Map ICx (IC2-IC9) to Peripheral Pin Registers for PIC24FJ256GA110 Family. IC1 can only be mapped to RP0-RP31 |
PIC24FJ256GA110 Family |
|
SIM-646 |
Triple Comparator in PIC24FJ256GB110 family and PIC24FJ256GA110 family doesn't function as expected |
PIC24FJ256GB110 family (PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106), and PIC24FJ256GA110 family (PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106) |
|
SIM-650 |
Cannot Map ICx (IC2-IC9) to Peripheral Pin Registers for PIC24FJ256GB110 Family. IC1 can only be mapped to RP0-RP31 |
PIC24FJ256GB110 Family |
|
SIM-651 |
[PIC16F747]CCP2 interrupt is only triggered when CCP2MUX is set to RC1 and stimulus appears on RC1. When CCP2MUX is set to RB3 and stimulus appears on RB3, nothing happens. |
PIC16F747 |
|
SIM-653 |
[OC w/ Dedicated Timer] The OCxTMR register never increments in PIC24FJ256GB110, PIC24FJ256GA110, PIC24FJ64GA104 & PIC24FJ64GB004 families |
PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106, PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106, PIC24FJ32GA102/104, PIC24FJ64GA102/104, PIC24FJ64GB004/002, PIC24FJ32GB004/002 |
|
SIM-654 |
[OC w/ Dedicated Timer] With OCSIDL bit cleared, code execution doesn't branch to OC9 ISR even if OC9IF is set in PIC24FJ256GB110/GA110 family; when OCSIDL bit is set, OC9 ISR is never exited; it works fine for OC1 through OC8 |
PIC24FJ256GB110 family (PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106), and PIC24FJ256GA110 family (PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106) |
|
SIM-656 |
PIC18F4455 should have ECCP module support, but only CCP is implemented. |
PIC18F4455,PIC18F4610 |
|
SIM-657 |
for PIC18F4480 and PIC18F4580, ECCP2 module is implemented although there is none, and ECCP1 is not implemented. |
PIC18F4480, PIC18F4580, PIC18F448, PIC18F458, PIC18F4585,PIC18F4680,PIC18F4682,PIC18F4685 |
|
SIM-660 |
Digital IO for PORTs A,B, and C are not consistent with datasheet or hardware debugger. |
PIC18F13K50 |
|
SIM-661 |
In PIC24FJ64GA104 family (DS39951A) and PIC24FJ64GB004 family (DS39940A), the Output Compare module implementation is not correct - these devices have OC w/ Dedicated Timer, and not the conventional OC |
PIC24FJ32GA102, PIC24FJ32GA104, PIC24FJ64GA102, PIC24FJ64GA104, PIC24FJ64GB004, PIC24FJ64GB002, PIC24FJ32GB004, PIC24FJ32GB002 |
|
SIM-662 |
[OC w/ Dedicated Timer] Output Compare in Cascade Mode doesn't work in PIC24FJ256GB110 family and PIC24FJ256GA110 family |
PIC24FJ256GB110 family (PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106), and PIC24FJ256GA110 family (PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106) |
|
SIM-663 |
Resets in SIM (other than Processor Reset) did not reset SR to 0x0000, it remained unchanged |
dsPIC30F, dsPIC33F, PIC24F, PIC24H, etc. (A lot of green lit device) |
|
SIM-664 |
See warning "CORE-W0001: Illegal opcode or unitialized WREG has caused a reset" for initialized working registers |
PIC24FJ64GA004 (perhaps other devices too) |
|
SIM-668 |
[OC w/ Dedicated Timer] In PIC24FJ256GB110/GA110 families, in PWM mode w/ Fault inputs operating in Cycle-by-Cycle mode, OCFLT0 bit of OCxCON1 must get cleared automatically at the end of each PWM Cycle unless the Fault is still active |
PIC24FJ256GB110 family (PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106), and PIC24FJ256GA110 family (PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106) |
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SIM-669 |
12F629 has incorrect W/R and POR settings for TRISIO. TRISIO4 and TRISIO5 are always clear and unable to be changed in SIM. Using ICE2K and PCM12XB0 TRISIO 0-5 are able to be changed and default to 1. |
PIC12F629 |
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SIM-671 |
[OC w/ Dedicated Timer] Output Compare in PWM mode with Fault control doesn't work correctly in PIC24FJ256GB110/GA110 families |
PIC24FJ256GB110 family (PIC24FJ256GB110/108/106, PIC24FJ192GB110/108/106, PIC24FJ128GB110/108/106, PIC24FJ64GB110/108/106), and PIC24FJ256GA110 family (PIC24FJ256GA110/108/106, PIC24FJ192GAB110/108/106, PIC24FJ128GA110/108/106) |
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SIM-672 |
SIM did not trigger CN Interrupts for CN32-CN84 |
PIC24FJ256GA110 Family |
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SIM-673 |
OSCCON (IOLOCK) and FOSC (IOL1WAY) bits did not Function as Expected |
PIC24FJ256GA110 Family |
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SIM-674 |
RC12 and RC15 should function as port I/O only when Primary Oscillator / EC mode is (POSCMD = 11 or 00) |
PIC24FJ256GA110 Family, PIC24FJ256GB110 Family |
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SIM-675 |
Timer 1 gated mode increments when T1G is 1 or 0 even though T1GE bit is set. |
PIC16F785,PIC16HV785 |
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SIM-676 |
[PIC24FXXKAXXX] In Output Compare in PWM mode with Fault Protection input, a fault condition does not occur when a logic '0' is detected on the OCFA pin |
PIC24F04KA200, PIC24F04KA201, PIC24F08KA101, PIC24F08KA102, PIC24F16KA101, PIC24F16KA102 |
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SIM-683 |
[PIC24FXXKAXXX] In Output Compare module, the state of the OC pin when the device wakes from sleep must be same as its state before the device entered sleep mode |
PIC24F04KA200, PIC24F04KA201, PIC24F08KA101, PIC24F08KA102, PIC24F16KA101, PIC24F16KA102 |
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SIM-684 |
[PIC24FXXKAXXX] - Comparator module in PIC24F04KAXXX, PIC24F08KAXXX and PIC24F16KAXXX families doesn't function as expected |
PIC24F04KA200, PIC24F04KA201, PIC24F08KA101, PIC24F08KA102, PIC24F16KA101, PIC24F16KA102 |
|
SIM-685 |
Triple Comparator module in PIC24FJ64GB004 family and PIC24FJ64GA104 family doesn't function as expected |
PIC24FJ32GA102, PIC24FJ32GA104, PIC24FJ64GA102, PIC24FJ64GA104, PIC24FJ64GB004, PIC24FJ64GB002, PIC24FJ32GB004, PIC24FJ32GB002 |
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SIM-686 |
SFR TRISB (maybe others?) does not work for Register Trace in stimulus. Message "CORE-W0008: SFR TRISB does not support response file attachment" is shown in output window upon hitting "apply". |
PIC16F767, 24HJ256GP210, PIC18F25K20... probably all |
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SIM-694 |
Unexpected behavior PORTB (RB12 and RB15) for PIC24FJXXGA102 |
PIC24FJXXGA102 |
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SIM-699 |
Unable to use TMRx (other than its default - TMR3) for Input Capture with Dedicated Timer for PIC24FJXXGA1 and GB |
PIC24FJ64GB004 and PIC24FJ64GA104 families |
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SIM-700 |
In PIC24FJ256DAXXX and PIC24FJ128DAXXX Family of devices the UART3 and UART4 module implementation is missing |
PIC24FJ256DA210, PIC24FJ256DA206, PIC24FJ256DA110, PIC24FJ256DA106, PIC24FJ128DA210, PIC24FJ128DA206, PIC24FJ128DA110, PIC24FJ128DA106 |
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SIM-701 |
Incorrect RA6 and RA7 Behavior for CONFIG1 <FOSC> = 0x100 for PIC16F193X Devices |
PIC16F193X |
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SIM-702 |
PIC10F2XX has incorrect timing for AD conversion. It takes too long. |
PIC10F220 |
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SIM-703 |
PORTA bit 2, 3, and 5 should only be I/O pins for certain conditions for PIC24F04KA201 and PIC24F16KA102 Family |
PIC24F04KA201 and PIC24F16KA102 Family |
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SIM-705 |
When Debugger->Settings->UART is enabled, Register Trace does not function for UART Registers such as TXREG. Only one or the other can be used. |
PIC16F914 as an example, probably all. |
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SIM-706 |
When using UART Registers (TXREG) in Register Trace, only 7-bits are output into the .txt file. This should be 8-bits. |
PIC16F914 example, affects all |
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SIM-707 |
Reseting device while T08BIT is cleared will reset the SFR bit T08BIT to 1, but the functionality will continue as if it was cleared until it has been toggled in code or the project has been rebuilt. |
PIC18F4680 |
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SIM-708 |
[PIC18F13K50] Default value of ADCON1 is not correct when Simulator is selected as debugger. |
PIC18F13K50 |
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SIM-709 |
PIC16F19XX devices have implemented a four word flash write write. The datasheet indicates an eight word flash write. |
PIC16F19XX |
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SIM-711 |
APFCON register is ineffective at changing the function of P1A, P1C, and P1D. |
PIC16F18XX |
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SIM-712 |
RABIF is set upon stimulus of RB/RA pin regardless of the state of IOCA/B. |
PIC18F13K22 |
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SIM-713 |
Unable to read/write to PORTB and incorrect ANSx behavior for PIC24FJ256DA210 and PIC24FJ256GB210 family |
PIC24FJ256DA210 Family and PIC24FJ256GB210 Family |
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SIM-716 |
RPINRx/RPORx Should Not Change When OSCCON #IOLOCK is set |
PIC24FJ256DA210 Family |
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SIM-717 |
WDT for Cooper devices does not have full implementation of WDTPS. 1:65536 is the last post scalar implemented, anything afterwards is not. |
PIC16F19XX |
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SIM-718 |
RC12 and RC15 should function as port I/O only when Primary Oscillator / EC mode is (POSCMD = 11 or 00) for PIC24FJXXXDA Devices |
PIC24FJ256DA, PIC24FJ256GB110 Family |
|
SIM-723 |
Unexpected ICxF trigger delay for PIC24FJ256DA and PIC24FJ256GB Family Devices |
PIC24FJ256DA210 and PIC24FJ256GB210 Families |
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SIM-725 |
RA5 pin can not be turned to digital mode for PIC18F87K22 device |
PIC18F87K22 |
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SIM-726 |
AD1PCFGL and AD1PCFGH SFR are not defined in PIC24FJXXXDAXXX devices. |
PIC24FJ256DA210, PIC24FJ256DA206, PIC24FJ256DA110, PIC24FJ256DA106, PIC24FJ128DA210, PIC24FJ128DA206, PIC24FJ128DA110, PIC24FJ128DA106 |
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SIM-729 |
RESET instruction is not recognized by code coverage even when it is executed. PIC18F458 |
PIC18F458 |
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SIM-730 |
Timer0 stops working when entered into Idle mode for PIC18[Enhanced] family of devices |
PIC18 [Enhanced] family of devices |
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SIM-732 |
If you put SFR RPINR16 = 0x1F then any synchronous stimulus will cause a stimulus error upon hitting "apply" |
PIC18F46J50, 65J50 |
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SIM-733 |
Using WUE (Wake-Up Enable) with UART does not wake up if stimulus is applied to RX pin. |
|
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SIM-734 |
When TMR1 is ON, and you set TMR1 to 0xFFFF the rollover that happens will not trigger the TMR1IF bit. |
PIC16F630 |
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SIM-735 |
WDT event is not triggered, whereas with the same code in 8.53 an event is. |
PIC16F526 |
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SIM-737 |
[HI-TECH PIC18 Compiler] The Simulator hangs on the delay fn, when trying to step in to the code |
PIC18F2620 |
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SIM-738 |
When IOCBN and IOCBP are both clear, a positive or negative edge should not affect the IOC flags. In the simulator IOCIF still gets set. |
PIC16F1827 |
|
SIM-740 |
Setting bit 1 of CCP3CON causes MPLAB to crash. |
PIC18F45K22 |
|
Key |
Summary |
Device Affected |
|
SIM32-58 |
Minimum Tad time warning is incorrect in simulator for PIC32 devices |
PIC32 |
|
SIM32-99 |
PIC32: Latency for 16, 24 and 32 bit Divide operation do not match datasheet in simulator for PIC32 devices. There is a minor difference |
PIC32MX family |
|
SIM32-100 |
PIC32: MUL, MADD, MULT , MSUB etc gives incorrect result if interrupt occurs at certain stage of pipe line in simulator for PIC32 devices |
PIC32MX Family |
|
SIM32-101 |
PIC32: Latency for 32*32 MUL operation is 1 instruction cycle less than the expected for PIC32 simulator |
PIC32MX Family |
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SIM32-102 |
PIC32: Back to back 16*16 or 32*16 MUL operation cause pipe line stall in simulator PIC32 devices |
PIC32MX Family |
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SIM32-105 |
PIC32: Analog comparator expects its input pins to be configured as 'Digital' pins to responds to inputs in simulator for PIC32 devices |
PIC32MX Family |
|
SIM32-106 |
PIC32: OSCCON register fields such as PLLODIV, PBDIV, PLLMULT are not loaded from device configuration register on reset for PIC32 device |
PIC32MX Family |
|
SIM32-109 |
PIC32: Enhancement request to implement unlock sequence for software reset for PIC32 devices in simulator |
PIC32MX Family |
|
SIM32-111 |
PIC32: Sleep/Idle mode: External Interrupt or Peripheral Interrupt is not getting generated when device is in low power mode for PIC32 devices |
PIC32MX Family |
|
SIM32-112 |
PIC32[WDT]: Under Simulator debugger settings , reset on WDT time out and WDT Time out field settings are not saved and reverts back to default for PIC32 devices. |
PIC32MX Family |
|
SIM32-121 |
EICSS filed of SRSctl register is not getting updated when interrupt get generated in SIM32 for PIC32 devices |
PIC32MX family |
|
SIM32-125 |
Read Pointer Update Action on input capture buffer does not match FRM for PIC32 devices |
PIC32MX family |
|
SIM32-127 |
PLL Lock bit of OSCCON register is not being set when clock source with PLL is set in configuration register for PIC32 devices |
PIC32MX Family |
|
SIM32-145 |
[Stimulus] SPI1 signals and PINs are missing in the stimulus for PIC32MX-100 PIN USB devices |
PIC32MX4XXL Family devices |
|
SIM32-164 |
Software reset operation does not reset the execution to reset vector on certain condition for PIC32 devices. Also, RSWRST is not write protected and unlock sequence is not implemented |
PIC32MX |
|
SIM32-165 |
LW instruction does not stall the pipe line even if instruction following LW is the consumer of result of LW for PIC32MX devices |
PIC32MX |
|
SIM32-170 |
CLRASM bit of ADC control register, has no effect on terminating the auto-sample after first sequence is completed, for PIC32 devices |
PIC32MX |
|
SIM32-180 |
External INT3 and INT4 cannot be simulated for PIC32MX675F256H, PIC322MX775F256H, and PIC32MX775F512H due to missing identifier in stimulus |
PIC32MX675F256H, PIC32MX775F256H, and PIC32MX775F512H |